The present inventive concept relates to semiconductor devices, and more particularly, to a semiconductor device including a plurality of circuits and a bus connecting the circuits to one another, and a method of operating the semiconductor device.
Semiconductor devices may include a plurality of circuits constituted to perform various functions. The plurality of circuits may be embodied in one chip in the form of a system-on chip, or may be embodied in a plurality of different chips. The various circuits are connected to one another through a bus or an interconnection line, and are configured to communicate with one another through the bus or interconnection line to access a target circuit.
With the advancement of technology, the number of functions embodied in semiconductor devices has increased, and consequently the number of circuits in semiconductor devices and the complexity of buses or interconnections connecting the circuits to each other have increased. Because of such complexity, it has become more difficult to effectively schedule and adjust the order of work in a bus and/or interconnection based on priority. As a result, latency when accessing a target circuit through a bus or an interconnection may increase. There is thus demand for a new bus or a new interconnection that supports scheduling capable of processing work) having higher priority first, to reduce latency with respect to urgent requests.